1. Field of the Invention
The present invention relates to the field of charge pumps.
2. Prior Art
Charge pumps are used to generate voltages beyond the supply rails (primary power source) of a system. In integrated circuit (IC) design, they are especially used in non-volatile memory technologies where very large voltages, compared to the input supply voltages, are required for programming and erase. They are also used in analog circuits to derive negative voltage supplies (allowing the IC only to require a positive connection to the outside world) and to derive large voltages locally when the IC is to be used in an especially low voltage system (e.g. a battery powered system). In digital circuits, charge pumps are sometimes used to reduce the supply voltage (and hence supply current) in certain high-activity areas of the IC and to derive negative voltages for biasing substrates in order to reduce leakage currents. Those skilled in the art will recognize that these examples are just examples, and that the potential uses for charge pumps are considerably wider and more varied than presented here. Furthermore, the following descriptions are intended to be considered from the point of view of implementation on an integrated circuit, although those skilled in the art will recognize that the invention is not limited to integrated circuit implementation.
FIG. 1a shows the basic components of a prior art charge pump. One of ordinary skill in the art will appreciate that there are other basic configurations of charge pumps, and that the scheme of FIG. 1a is used by way of example only, and is in no way limiting of the scope of the present invention to this general charge pump structure. As shown in FIG. 1a, a ‘flying capacitor’ CF, under the control of clock signal Φ (FIG. 1b) controlling switches SW1 and SW2, is alternately connected between Vdd and Gnd (the system power supplies), and Vdd and node HV. The capacitor CR coupled between HV and Vdd is known as a ‘reservoir’ capacitor and, over many oscillations of Φ, becomes charged to Vdd. Hence, with no load current ILOAD, node HV charges to a potential of 2Vdd with respect to node Gnd. It will be appreciated by those with ordinary skill in the art that many charge pump stages like that of FIG. 1a or of older designs can be cascaded to achieve output voltages in excess of 2Vdd.
Generally, some load current, ILOAD, is present on node HV. This causes a ‘sawtooth’ waveform (FIG. 1c) of amplitude VRIPPLE on node HV as the charge on capacitor CR is continuously removed by the load, yet is replenished only periodically from the flying capacitor. The average output voltage, VAVERAGE, is therefore load dependant and something less than the maximum achievable 2Vdd. This ripple is usually undesirable, and can be minimized by several approaches:
1. For a given load current, increasing the size of the reservoir capacitor CR proportionally decreases the ripple, but also proportionally increases both the area (CR is generally by far the largest component in such a charge pump) and the turn-on time (number of cycles of Φ required to initially charge node HV to its target voltage of 2Vdd).
2. It is very common to attempt to provide a more continuous supply of charge from the flying capacitor. This can be achieved for instance, as shown in FIG. 2a, by splitting the flying capacitor into two devices with switches SW1 through SW4 driven by clock phases 180 degrees apart (depicted as Φ and ΦB in FIG. 2c). Still the output HV contains substantial ripple, as shown in FIG. 2b. Clearly, if capacitor CF were split into an infinite number of devices driven by an infinite set of clocks phase shifted from Φ by 0° to 360°, then the ripple would be zero. However, note that as the number of flying capacitors is increased, so does the number of switches. Complexity in the clock generation circuits and the inefficiency introduced by manipulating the switches prevents more than a very few phase-shifted flying capacitors being used.
Another approach is to regulate the output voltage in some way. Many regulator designs are well known in the art, such as disclosed in U.S. Pat. No. 5,877,948. FIG. 2d shows a prior art double flying-capacitor system like that of FIG. 2a, but further including an output regulator. Without exception, all such regulator designs require HV to be at a higher potential than Vout (see FIG. 2b). This immediately introduces significant inefficiency in the pump design. Furthermore, it means that the maximum useable voltage at the output HV must be lower than the maximum voltage permitted by the breakdown of the fabrication process. As breakdown voltages are becoming smaller and smaller with decreasing process geometries, this can be a significant disadvantage.
Returning to FIG. 2a, consider the nature of the clocks Φ and ΦB. There are several different possibilities:
1. Continuous frequency, amplitude =Vdd. In this scheme (the simplest scheme), if the load current is constant, an average voltage will result at node HV such that the average charge removed from the capacitor CR by the load in time Δt is equal to the average charge supplied by the flying capacitors CF1 and CF2 in the same time period Δt. This is an open loop system. If the load current changes, the output voltage at node HV responds to compensate and keep the above equality true. Therefore, higher load currents reduce the voltage at HV, lower load currents increase it. Similarly, changes in the supply voltage Vdd directly affect the achieved output voltage. For varying loads, this is a very inefficient approach, yet is very common (see Dickson, IEEE Journal of Solid State Circuits, Vol SC-11, No. 3, June 1976, pp 374-378). Often, a voltage sensitive current clamp (e.g. zener diode) is used to regulate the output of such a charge pump by dumping the excess current supplied by the charge pump, resulting in a very low efficiency.
2. Continuous frequency, amplitude <Vdd. In this scheme, a reference voltage is used instead of Vdd to ensure that the amplitude of the clocking signal is independent of Vdd. This ensures that the output voltage at node HV is independent of supply voltage variations, but it is still sensitive to load current variations as described in technique 1 above.
3. Continuous frequency, variable amplitude. Here, an indicative circuit parameter is monitored and the amplitude of the clocking waveforms modulated accordingly to maintain a constant voltage at node HV. Typically, the voltage on node HV is monitored itself (see U.S. Pat. No. 6,300,820), although other parameters can be observed (see U.S. Pat. No. 6,002,630).
4. Variable frequency, fixed amplitude. Here, an indicative circuit parameter is monitored and the frequency of the clocking waveforms modulated accordingly to maintain a constant voltage at node HV. Typically, once again, the voltage on node HV is monitored (see U.S. Pat. Nos. 6,115,272 and 6,310,789,).
5. Variable frequency, variable amplitude. Techniques 3 and 4 above can be combined, as demonstrated in U.S. Pat. No. 6,188,590.